Dielectrically isolated island structures are commonly employed in integrated circuit architectures for supporting a variety of circuit components, such as bipolar transistor devices, junction field effect devices, DMOS circuits, etc. In a typical (NPN) bipolar configuration, shown in FIG. 1, a high impurity concentration (N+) buried subcollector region 11 is formed at the bottom of an island (e.g. silicon) region 10 that is dielectrically isolated from a support substrate 12 (e.g. silicon) by means of a layer of insulator material (e.g. silicon oxide) 14 therebetween. The thickness of subcollector region 11 may be on the order of five to fifteen microns, depending on how heavily doped it is and to what magnitude of Dt product it is subjected during wafer processing. The thickness of the N- island 10, in the upper surface of which a P base region 15, an N+ emitter region 16 (formed in base region 15) and an N+ collector contact region 17 are formed, must be sufficiently large to support the base-collector depletion region layer without causing the peak field in the depletion layer to exceed the field at which the transistor goes into collector-emitter breakdown with the base open circuited, BVCEO. For a 100 V BVCEO NPN device having an HFE of 400, an N-thickness beneath the base, on the order of ten microns, is required. The minimum resistivity for such a device is about 10 ohm-cm. With a collector-base junction depth in the range of two to eight microns, minimum island thickness will therefore be relatively large (on the order of 22 microns) and therefor costly to manufacture.
The large size of such thick islands is also due to the fact that their sidewalls are sloped or inclined as a result of the application of an anisotropic etchant through a photolithographic mask the size of which defines the bottom of the island. The minimum front surface dimension of the finished island cannot be less that the minimum bottom dimension plus two times cot a times the island thickness, where a is the angle between the island sidewall and the island surface. This angle for typical dielectric isolation fabrication techniques using &lt;100&gt; oriented wafers is on the order of 55 degrees. As a consequence, in the case of the above-referenced island having a minimum thickness of 22 microns, the minimum island width will be 31 microns, plus a minimum bottom dimension on the order of 10 microns, yielding a minimum lateral island dimension of 41 microns for a 100 V buried layer NPN transistor. As this width is considerably greater than that normally attributed to small components, it effectively represents wasted space.